An integrated debugging environment for FPGA computing platforms

Large-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. In our approach to mitigate this problem, the concepts of variables and process control are brought into the FPGA hardware domain. Declarations made in the design environment are translated into logic inserted automatically into the hardware implementation. Variables provide full read/write access to hardware signals during runtime, complete with same-cycle, dynamically definable assertion checking. System data is cached via attached DRAM, providing deep variable history and the ability to ldquorewindrdquo system state. Process execution can also be controlled by the user manually or through the declaration of breakpoints. All debugging controls are available via a remote graphical user interface, which also supports back-annotation in the input design for improved data visibility and comprehension. Empirical examples have shown the logic overhead for the above functionality to be approximately 66 slices per 16-bit variable with full assertion checking on a Virtex-II Pro device, plus the fixed requirements of the debug controller and memory interface.