DVFS Aware Techniques on Parallel Architecture Core (PAC) Platform

Rapid developments of multimedia and communication technologies enrich the applications of portable devices. However, design flexibility and low power are two important criteria for real-time system development. In this paper, a DVFS-aware implementation is introduced to demonstrate intelligent dynamic voltage and frequency scaling (DVFS) technique on dual-core PAC Platform. The power management of DVFS technique is verified with the H.264/AVC decoder example which can save 46% of power consumption.