Radio Processor - A New Reconfigurable Architecture for Software Defined Radio

Performance required by "software defined radio (SDR)" poses many challenges in real-time applications because of their high computational complexity and therefore, designing a high performance SDR with high degree of flexibility becomes a major issue. While the fastest programmable DSP processors are unable to meet the speed requirements for SDR, system on chips (SOCs) are also not suitable because of their limited flexibility. Recently, FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions. Since , the major building blocks for SDR are the signal processing functions, FPGAs are becoming possible hardware platform for SDR. However, FPGAs are not optimized for radio applications and because of their LUT based approach, they can not offer the highest possible performance at the lowest silicon cost for a given signal processing function. This paper addresses these issues by introducing a new "reconfigurable radio processor" for implementing SDR. The architecture was validated on Xilinx Virtex IV FPGA.