A Survey on System-Level Techniques for Power Reduction in Field Programmable Gate Array (FPGA)-Based Devices

With growth demands to untethered embedded systems, e.g. sensor nodes, in the flexibility, performance, product longevity, areas, and decreasing time-to-market (TTM), programmable logic devices may allow covering lack of suitable processing units. Decrease in the feature transistor sizes allows producing smaller programmable devices and providing more computational power. However, such shrinking of feature sizes introduces higher power lost (static power). Moreover, programmable devices are clocked with higher frequencies due to the performance demands increase that introduces additional power consumption. Therefore, there is a need for techniques that allow for substantial power reduction and being achievable on the higher levels of the designing process. In this paper, we address means of the dynamic power consumption reduction on the system-level. This is envisaged that proposed techniques may allow achieving substantial power consumption savings with negligible hardware overheads while maintaining the energy per operation.