A study of jitter effects in nm-FPGA based on various physical and electrical quantities

Achievements in semiconductor nanotechnology have enabled the design of advanced devices with higher performance. However, implementation of modern nanotechnology devices requires paying strict attention to parasitic effects, such as jitter which is caused by switching the entire device core logic elements (Core jitter) as well as the output buffer jitter caused by switching the inputs and outputs (I/O) of the device. These timing variations decrease the timing margin and limit the achievable data rate of an integrated circuit (IC). This paper presents a study of the jitter effects due to core noise and I/O noise on field programmable gate arrays (FPGAs) manufactured using both 90-nm and 65-nm process technologies respectively. This paper evaluates the impact of the following factors on Core Jitter: aggressor location in a device; aggressor switching frequency, and aggressor pattern type and switching core logic percentage. The timing variations based on switching I/O are also studied. The results can assist electronic system designers with methods of reducing Core jitter and I/O jitter, and thus achieve error-free design goals.