Clearphone : A 0.9 V 96 μW digital hearing aid system

A low power fully operational digital hearing aid chip, named Clearphone, is proposed and implemented. To achieve both the high energy efficiency and flexibility, it adopts the enhanced adaptive-SNR analog front-end, the dedicated DSP and the heterogeneous Σ-Δ DAC. Implemented in a 0.18 μm standard CMOS process with a 0.9 V supply voltage, the power consumption of the overall system is only 96 μW. To achieve high flexibility, the combined gain control (CGC) preamplifier and dedicated DSP are presented. The peak SNR of the system is 79 dB and the active area is 2.8 mm × 1.1mm.