A Four Quadrant CMOS Analog Multiplier Based on the Non Ideal MOSFET I-V Characteristics

This paper concerns an analog CMOS multiplier based on a novel approach to compensate for non idealities of the MOSFET square law approximation. A numerical algorithm has been implemented to find the optimum sizing of the active devices, starting from the process characteristics. The effectiveness of the proposed configuration has been demonstrated by means of electrical simulations performed on a prototype cell, designed using 0.32 mum - 3.3 V CMOS devices from the STMicroelectronic process BCD6s.