A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Based on the approach, the low-cost hardware architecture with digital image scaling is designed under the real-time requirement. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. The presented architecture is implemented on the Virtex-II FPGA, and the VLSI architecture has been successfully designed and implemented with TSMC 0.13 mum standard cell library. The simulation results demonstrate that the high performance architecture of extended linear interpolation at 267 MHz with 26200 gates in a 452times452 mum
²
chip is able to process digital image scaling for HDTV in real-time.