A designer friendly 45nm high performance technology with in-situ C-doped e-SiGe & dual stress liner in SRAM

A 45 nm high performance technology with 11 level metallization is presented for SOC applications. High performance and density are maintained through new process optimizations that allow the use of less restrictive layouts by eliminating defect generation from strain enhancing processes. Additionally, technology modeling has been made simpler through optimization of key processes to minimize context dependences while simultaneously providing a competitive technology. High drive currents of 1150 uA/um and 720 uA/um are obtained for nMOS and pMOS, respectively at 1.0 V and Ioff of 100 nA/mum. The first yielding SRAMs incorporating both in-situ C-doped e-SiGe and dual stress liner (DSL) in the SRAM are demonstrated.