Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications

This work highlights the new bulk
⁺
technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to T
_si
= 8 nm) and thin BOX (T
_box
= 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (W
_design
/L
_gate
= 90 nm/40 nm) at V
_dd
= 1.1 V and I
_off
< 2 nA/ mum is as high as 1298 muA/ mum for nMOS and 663 muA/ mum for pMOS. In addition, reliability, noise and 6T-SRAM bit cells down to 0.249 mum
²
are characterized. Significant improvements with respect to conventional bulk technology are demonstrated.