A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication

A 21-channel 8 Gb/s transceiver is implemented in a 90 nm CMOS technology. 168 Gb/s uncoded data transmission with 3.6 ns latency is achieved with 4-tap FFE, receiver equalization, jitter tolerant CDR and low jitter PLL. Measured bathtub plots for 80 cm FR-4 backplane indicate BER<10
^-15
with 0.11 UI phase margin at the nominal power consumption of 160 mW/ch.