A 2.1mW/3.2mW delay-compensated GSM/WCDMA ΣΔ analog-digital converter

A technique to compensate for the harmful excess loop delay in a continuous time SigmaDelta analog-digital converter is presented. With no extra power consumption or area penalty the technique is suitable for variety of applications employing continuous time SigmaDelta analog-digital converters. This work presents a dual mode SigmaDelta ADC for GSM/WCDMA applications with DR of 86 dB/63 dB for 100 KHz/1.92 MHz in a 65 nm CMOS technology with power consumption of 2.1 mW/3.2 mW.