A fully logic-process-compatible, 3-transistor, SESO-memory cell featuring 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention

A 1-kb memory-cell array composed of single-electron shut-off (SESO) cells was fabricated with the 90-nm logic process for the first time. It features a 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention. In addition to a logic-compatible cell structure and a write-data caching scheme, a backup latch circuit with SESO transistors for logic application was also proposed.