High-Level Modeling and Exploration of Reconfigurable MPSoCs

This paper presents a novel methodology for modeling partially dynamic reconfigurable hardware at transaction-level. We cover the lack of tools and mechanisms for the design of reconfigurable logic at system-level and for the exploration of the different configurations of such architectures. The presented mechanisms have been implemented in ReSP, a transaction-level simulation platform especially targeted to multi-processor embedded architectures. In our methodology we allow the definition of the reconfigurable functionalities through scripted languages, therefore the switching of any software function for a hardware one, the modeling the configuration delays, area use, etc., can be easily performed (even at runtime). Overall, the methodology enables a powerful exploration of the system's functionalities by switching between hardware and software components. Results show that our solution brings flexibility, accuracy, and fast alternative evaluation, as compared with RTL solutions, in the development and design of dynamically reconfigurable embedded systems.