A new algorithm for cyclic and pipeline data conversion

An algorithm is proposed for digital-to-analog conversion. The conversion starts with the most significant bit. This algorithm can be implemented using unity-gain buffers and thus permits high-speed data conversion. Switched-capacitor D/A and A/D converter architectures based on this algorithm are described, and experimental results are presented to demonstrate its validity. Error analysis shows that a conversion accuracy of at least 9 b is obtainable with a monolithic implementation. Computer simulations indicate that video-frequency operation may be possible if fine-line CMOS, bipolar, or BiCMOS technology is used.<
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