11 Gb/s limiting amplifier flip-chip assembled in a BGA package

A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz f
_T
SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz effectively filtering integrated noise to obtain low input sensitivity. A 21 GHz output bandwidth necessary for extremely fast rise times is obtained by incorporating output buffer transistor, ESD and pad parasitics into on-chip transmission lines (TLs) and by using flip chip assembly and ball grid array packaging techniques.