A 0.5 V area-efficient transformer folded-cascode low-noise amplifier in 90 nm CMOS

We present a low-voltade transformer folded-cascode CMOS low-noise amplifier (LNA). We reduce the chip area of the LNA by coupling an internal inductor and load inductor, and show the effects of the coupling on the LNA by using analytical expressions. The LNA, implemented with 90-nm digital CMOS technology, occupies 0.21 mm
²
and achieves S
11
≫ −10 dB, NF = 2.7 dB and S
21
= 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW from a 0.5 V supply. The proposed a power consumption of 1.0 mW from a 0.5 V supply. The proposed LNA can replace the conventional folded-cascode LNA.