A 0.13-μm CMOS Σ-Δ frequency synthesizer with an area optimizing LPF, fast AFC time, and a wideband VCO for WCDMA/GSM/GPRS/EDGE applications

Use This paper presents a fully integrated fractional-N frequency synthesizer (FNFS) with an area optimizing low pass filter (LPF), fast adaptive frequency calibration (AFC) time, and a wideband on-chip LC voltage-controlled oscillator (VCO) for WCDMA/GSM/GPRS/EDEG transceivers. The FNFS employs a staked structure of MIM and MOS capacitors for LPF to economize the area. Fast AFC time is realized by using the prescaler output signal as a discriminating clock. A 3-bit 3rd order Σ-Δ modulator serves as a fractional engine. Phase switching type prescaler is used to reduce the quantization noise of Σ-Δ modulator. A fast switching CP is introduced. LC VCO utilizes bond-wire inductors with high Q-factor and a small area. Digitally controlled crystal oscillator (DCXO) provides a reference signal of high spectral purity. A prototype has been implemented in 0.13 μm CMOS technology. The measurements results show that the AFC time is less than 20-μs, in-band phase noise is −94dBc/Hz, and out-band phase noise are −123dBc/Hz at 400KHz offset frequency and − 145dBc/Hz at 3MHz offset frequency when the carrier frequency is 900MHz. Reference spur level is less than −75dBc.