An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4

A fully integrated 2.4GHz transceiver based on the IEEE802.15.4 specification has been designed using a 130nm CMOS technology. Concurrent system and design optimizations were required to reach an energy efficiency of 21.5nJ/bit in RX mode and 32.5nJ/bit in TX modes, respectively, at a data rate of 250kbit/s. The circuit includes a −5dBm transmitter, a −81dBm sensitivity receiver, an integer N PLL with 5MHz reference, a dual I/Q 3-bit ADC at 4MS/s, an analog RSSI with 8-bit ADC at 8kS/s and an integrated SPDT TX/RX switch to a 100 Ω differential antenna port. The chip consumes 5.4mW in RX mode and 8.1mW in TX mode under 1.2V.