A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture

A study of the latch-up robustness for a new power IC technology involving Si substrate/wafer modifications is presented in this paper. The results shown confirm that for dual-well CMOS technologies, changes in the substrate/epitaxial layer structure are a satisfactory way of improving power IC process capabilities without compromising the CMOS performance. Both simulation and experimental results are presented.