SystemVerilog implicit port enhancements accelerate system design & verification

The IEEE Std 1800-2005 SystemVerilog standard added new implicit port instantiation enhancements that help accelerate top-level composition of large ASIC & FPGA designs. This paper details the new .* and .name implicit port instantiation capabilities, the rules related to the use of these new enhancements, and how these enhancements offer concise RTL coding styles while enforcing stronger port-type checking.