A Power-Efficient Configurable Low-Complexity MIMO Detector

In this paper, we propose a power-efficient configurable multiple-input-multiple-output (MIMO) detector, supporting QPSK, 16-QAM, and 64-QAM with low complexity. The approach divides a large MIMO detector into two subsystems: a core detector and a residual detector. The core detector, a low-cost 2 times 2 V-BLAST with ML detector, is used to detect the first two significant outputs. This detector not only efficiently increases the reliability of the entire MIMO detector through its ML performance in mitigating error propagation but also reduces the computational complexity by its search space reduction capability to decrease the computation from
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is the constellation size). The residual detector is an ordered successive interference cancellation (OSIC) detector that detects the rest outputs. The results of bit-error-rate simulations demonstrate that the proposed detector significantly outperforms the OSIC detector. Furthermore, two complete ASIC implementations fabricated by 0.13- mu m 1P8M CMOS technology are presented. We show that the proposed detector, which is configurable from 2 times 2 to 6 times 4 MIMO configurations, has the lowest complexity compared to other fabricated works with 64-QAM demodulation. Moreover, the measured normalized power efficiency of 3.8 Mb/s/mW is shown to be the most power-efficient design compared with the designs of other fabricated works.