A numerical analysis of crack growth and morphology evolution in chip-to-packages nano-interconnections

The International Technology Roadmap for semiconductors (ITRS) has predicted that by the year 2007, integrated chip (IC) packages will contain feature sizes of 65 nm and an I/O pitch for the die-to-package interconnects approaching 80 μm. These will reduce even further in the next five years. The current approach of using surface mount technology and flip chip are mainly solder based and the lead and lead-free solder interconnects are known to fail mechanically as the pitch is reduced from 200 μm down to lower levels due to the thermal mismatch between the substrate and the chip. Although compliant interconnection could solve some of the mechanical issues, it is done at the expense of the electric performance.