Synthesis of a timing-error detection architecture

Delay variation can cause a design to fail its timing specification. Ernst in [5] observes that the worst delay of a design is least probable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their experimental results show significant performance (or power) gain as compared with the worst-case design. However, the architecture in [5] suffers the short path problem which is difficult to resolve. In this paper, we propose a novel error-detecting architecture to solve the short path problem. Our experimental results show considerable performance gain can be achieved with reasonable area overhead.