Low-voltage green transistor using ultra shallow junction and hetero-tunneling

A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling V
_dd
down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.