Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process

This paper report 85 V high-side LDMOS which is implemented in a conventional 0.3 5 um BCDMOS process using one additional mask. The process has no thermal budget modification but use simple additional implant step. Also it is completely compatible with the conventional BCDMOS process and has similar performances with 80 V SOI LDMOS.