Integration of high-k/metal gate stacks for CMOS application

Integration of high-k/metal gate stacks has been discussed in this paper. Pre-gate clean, interfacial oxide treatment, high-k and metal film deposition were investigated for optimized J
g
-EOT. Various approaches such as HF vapor clean, surface hydroxylation treatment, and metal gate modification (such as interface treatment and high density top layer) were employed to improve the electrical properties. Electrical characterization (C-V, I-V) and material analysis (TEM, XPS) were conducted to examine the effects of these approaches on high-k/metal gate stacks.