Enabling technologies for 3D chip stacking

This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10μm. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2μm to 5μm large copper TSV chains are presented with a TSV resistance <200mΩ. Substrate noise due to TSV is also considered by TCAD and SPICE simulations in order to define preliminary design rules.