Schottky Source/Drain CMOS Device Optimization with Dopant-Segregated NiPt Silicide

We have successfully demonstrated an optimized dopant- segregated Schottky (DSS) source/drain CMOS technology featuring 35 nm physical gate length and 1.2 nm gate oxide. Several important device characteristics, including sidewall gate junction leakage suppression, short channel effect (SCE) control, along with drive current performance, are all investigated in this work. Furthermore, we notice that halo implant process is indispensable for providing the wider process window, which is realized by compensating the sensitive dopant segregation implantation (DSI) process. Without any supplement of additional process-induced stress, the DSS N/PMOS drive current of 100 nA/um and 510 uA/um at I
_off
=100 nA/um and V
_dd
=1.2 V are obtained. Moreover, an 11% I
_on
improvement can be achieved in the optimized DSS NMOS.