Modeling and Analysis Method for Radiation-Induced Upsets in Modern IC Device Models

As the demand for complex functions to be performed in harsh environments such as space applications converges with continually diminishing IC feature sizes, the traditional methods of circuit design and evaluation break down. The traditional IC design flow is mostly concerned with electrical interactions, in some cases considering power and thermal effects. Proposed is a method for integrating radiation expertise into this traditional IC flow. Specifically, the effect of ionizing radiation upon transient performance of digital and analog circuits is targeted. The questions to be answered with respect to circuit radiation tolerance are very similar to those associated with typical electrical parasitics. In a typical IC design flow, a circuit is designed and layout performed, utilizing rules of thumb and given Design Rule Checking (DRC). With layout complete, the designer desires to know more; what parasitic effects exist, as a side effect of their design, which they did not consider. In the electrical domain, a parasitic extraction tool is utilized to perform this operation. The output of this tool, a netlist augmented with RLC parasitics, is then simulated and performance observed. The results are consulted, and parasitic effects are (hopefully) mitigated through layout/design modification. For radiation-induced effects, can the same be accomplished? The answer comes in three parts. First, rules that describe exactly what a radiation-induced parasitic effect in layout are required. Second, a tool to find these effects is needed. Finally, efficient simulation models that describe the effects are necessary.