An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL

DLL clock multipliers outperform their PLL counterparts in terms of phase noise because they have significantly less jitter accumulation [1,2,3]. Figure 25.2.1 shows the basic PLL and recirculating DLL. In the latter, the oscillator loop is periodically opened to let in a “clean” reference edge. It avoids the pattern jitter due to delaystage mismatch as seen normally in an edge-combining DLL. The remaining pattern jitter is due to static phase offset of the phase detector (PD)/charge pump (CP). This offset transfers to a phase discontinuity between the two edges that are substituted for one another [2]. As a result the clock spectrum shows severe reference spurs, as high as -37dBc in [1]. This is especially undesirable in applications like ADCs where clock spurs convolute with the spectrum of the input signal. By contrast, in a PLL, static phase offset introduces no direct phase discontinuity in the output clock. Nevertheless, it still causes a periodic ripple across the loop filter that modulates the oscillator. By tightening the filter, the ripple is filtered more, lowering the reference spur. However, this reduces loop bandwidth leading to less suppression of oscillator phase noise.