A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

A 450 ps access-time 512 Kb SRAM macro is fabricated in a 45 nm SOI technology. The macro is adapted for use as the principal growable embedded-SRAM block in a 45 nm ASIC library. We describe a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 58% reduction in read power consumption under constant voltage and frequency compared to the previous generation macro. Also described is a single-device dynamic-leakage-suppression scheme that reduces total leakage power consumption by 37% with no wake-up-cycle requirements.