A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

The proposed SDR downconverter is aimed for the DVB-H standard (470 to 862MHz) and for emerging cognitive radio applications in the 200-to-900MHz band, which suffer from 3rd and 5th harmonic mixing. An inverter-based RF-amplifier (RFA) drives a passive switched-capacitor (SC) core consisting of three stages. The first stage is effectively an oversampler, second stage consists of I/Q DT mixers for downconversion and the third stage is a low-pass IIR filter. The chip fabricated in a 65nm CMOS process occupies an active area of 0.36mm
²
. The noise and linearity performances are competitive with those of continuous-time mixers at reasonable power consumption, which shows the feasibility of the proposed architecture for a practical receiver front-end.