A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS

Three years into the global deployment of 3G cellular services, the need to provide a compelling user experience has made HSPA an indispensable catalyst for a substantial subscriber transition from 2G to 3G [1]. Data rates reaching the full potential of 3GPP R6 from cost-effective mobile terminals with competitive power consumption are more crucial than ever for the commercial success of 3G and future of cellular data communications. The computational intensity of some of the critical functional blocks such as the demodulator and turbo decoder has made today’s HSDPA receivers power hungry and costly even at only 3.6Mb/s peak rate. This work explores the improvement potential for the turbo decoder from a design perspective, in a similar thrust to our recent work on HSDPA receiver [2].