A novel PLL design method applied to grid fault condition

A novel three phase PLL (phase lock loop) design method was proposed based on variable period sampling delayed signal cancellation (DSC) method. This PLL can be used in grid fault condition. The influence caused by unbalanced grid voltage will be eliminated effectively through delayed signal cancellation. Variable period sampling was used to trace the frequency deviation and eliminate phase shift offset which is caused by frequency deviation. The amplitude, phase and frequency of both the positive and negative sequence voltage will be detected in double synchronous reference frame. The proposed method was verified by experiment results.