VLSI Design of Diminished-One Modulo $2^{n}+1$ Adder Using Circular Carry Selection

The diminished-one modulo 2
ⁿ
+1 addition is an important arithmetic operation for a high-performance residue number system. In this paper, we propose a new circular-carry-selection (CCS) technique for modulo 2
ⁿ
+1 addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. For actual VLSI implementation, the proposed modular adder can demonstrate its superiority of savings up to 39.5% in AreaxTime and 46.3% in TimexPower performances over those of the previous existing solutions under 180-nm CMOS technology. Finally, the chip area and the clock rate of CCS diminished-one modulo 2
¹⁶
+1 adder are 26746 mum
²
and 476 MHz, respectively.