Detection and Removal of Limit Cycles in Sigma Delta Modulators

Sigma delta modulation is a popular method for converting signals from analog to digital and vice-versa. However, sigma delta modulators (SDMs) may suffer from limit cycles, where the output bits may enter a repeating pattern. Current methods of preventing this phenomenon introduce unwanted noise, do not always succeed, and are often implemented when not needed. We present a more effective method for detecting and removing unwanted limit cycles. This method includes adding a small disturbance to the input, which destroys the periodicity of sigma-delta analog-to-digital conversion (ADC) modulator's output sequence and thereby removes the limit cycles. Compared with conventional methods this method is simpler to implement, and the SDM has less signal-to-noise ratio (SNR) penalty and a higher allowed input dynamic range. Various implementations of the limit cycle detection and removal schemes are described for feedforward SDMs. Results are reported which demonstrate the success of these methods.