A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with ${> }$8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.