Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

Clock and data recovery (CDR) circuits incorporating a bang-bang (BB) phase detector have been widely adopted in high-speed serial links due to their advantages in high speed implementations. However, the heavily non-linear nature of the BB phase detector makes the analysis of the CDR loop difficult. In this paper, we propose a new technique for accurate and efficient estimation of the bit-error rate (BER) for BB CDR circuits. The technique estimates the BER based on the spectral information of jitter and the jitter transfer characteristics of the BB CDR circuit. It eliminates the conventional BER measurement process and, thus, substantially accelerates the jitter tolerance test. In addition, this technique offers insights into the behavior of the non-linear CDR loop and the contribution of the jitter to the BER. We present simulation results that demonstrate the potential usefulness of the method.