High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures

Targeting to improving the efficiency of real-time Fourier transform computations with large input data sets, this paper presents the design and the VLSI implementation of 16 K, 64 K and 265 K complex points fast Fourier transform (FFT) systolic architectures. These organizations are deeply pipelined to maximize the operating frequency and follow the approach of decomposing the transforms into 64 -point FFT computations to minimize the buffer size between consecutive stages. The resulting organizations achieve real time performance on testing and observation applications. They include simple processing elements and they are scalable with respect to the operating frequency and data width. Validation on FPGA showed operation at 250 MHz and 125 MHz for the 16 K and the 64 K architectures with throughput lGs/s and 500 Ms/s respectively. The VLSI implementations of the proposed 16 K, 64 K and 265 K architectures achieve post-route clock frequencies of 352, 256.5, and 188 MHz respectively and they can sustain throughputs of 1.4 Gs/s, lGs/s and 188 Ms/s.