Emergence of double patterning and in particular self aligned double patterning for the 32nm half pitch and below

Summary form only given. The complete presentation was not made available for publication as part of the conference proceedings. The semiconductor industry is driven by consumer applications such as multimedia phones and digital media which all have voracious appetites for memory, particularly the emerging solid-state memory applications. Without continued geometric scaling, advancing these devices and applications won't be possible. Self-aligned double patterning (SADP) is a new technique that can enable the scaling of memory devices in the face of a serious lithography roadblock. SADP is the primary double patterning approach for flash memory, developed in part by Applied Materials, that is gaining rapid momentum due to its superior pattern (line width) control and because it allows chip makers to use their existing, proven factory equipment. SADP is particularly suited to regular one-dimensional repeated patterns such as those of NAND-flash memory devices; it has already become the manufacturing strategy for designs below 35nm. Several memory manufacturers have publicly announced they will use or consider using this technique for high volume production of 3x nm designs beginning in 2009. This level of commitment is a testament to the manufacturing necessity, viability and scaling extendibility of SADP; multiple sub-22nm SADP features and FLASH applications have been demonstrated. Furthermore, SADP, has shown extendibility beyond FLASH to DRAM as well as logic. Leveraging regular logic lay-out design methodologies called “gridded design rules”, SADP can provide design & manufacturing capability to the 15nm logic technology node (2x features) using existing 193nm immersion systems. Gridded design rules and SADP gives a strong pairing of design and manufacturing strategies, and provides a clear path to becoming a standard patterning methodology for the industry beyond Flash design.