A block access unit for 2D memory access

Many of the coding tools in the H.264/AVC video coding standard are based on 2D processing resulting in rowwise and column-wise memory accesses starting from arbitrary memory addresses. This paper discusses a low-cost hardware realization of these accesses on sub-word parallel processors. The proposed block access unit is placed between the processor and memory. It supports unaligned 2D block accesses according to several 2D access patterns. The 2D block accesses are pipelinable and they result in minimum number of memory accesses required to deliver the desired data.