A Vertical Capacitor Cell for ULSI DRAM's

The objective of this paper is to illustrate the design of a a new Vertical Capacitor (VC) Cell suitable for high density dRAM's. In order to have a low soft error rate and a signal level adequate for achievable sense amplifiers, while achieving a very high level of integration, cell storage charge Qs must remain high as the cells themselves shrink. This goal cannot be realized by using a conventional planar one-transistor cell beyond 1 Mbit, leading to suggestion of the trench capacitor cell (1,5).