CHMOS - The Emerging VLSI Technology

Recent evolution of memory technology from NMOS to CMOS has been driven by multiple requirements including power reduction, design simplification, soft error protection and ease of scaling. The first high performance CMOS technology was a P-well CMOS Static RAM technology where device scaling was combined with the placement of a poly load N-channel memory array in the P-well to give a family of high speed 4K/16K SRAMs with efficient die size low soft error rate and low power consumption. i This has become the preferred approach to SRAMI at the 64K density level.