A CMOS Pair-Transistor Array Masterslice

This paper describes an advanced CMOS masterslice LSI based on a new concept. The concept is characterized by the carpeting of active devices over the whole chip area and by having no pre-assigned wiring channel areas for routing. The interconnections are carried out on arbitrarily assigned channel areas, which are formed on unused active device areas. Therefore, a minimum channel area can be assigned for any type of logic function.