Scaling CMOS Technologies with Constant Latch-Up Immunity

High performance CMOS circuits can be realized by scaling device dimensions into the sub-micron range. However, this also improves the performance of the inherent parasitic bipolar transistors responsible for latch-up, and thus latch-up becomes a major problem in CMOS VLSI technologies. This paper deals with the effect of scaling CMOS circuits on latch-up, and proposes a means of understanding these effects in terms of scaling theory. In the past, techniques for suppressing latch-up in small geometry CMOS devices have been described (1,2], but these approaches have been largely ad hoc in nature. This work uses the proposed description of latch-up to provide a systematic scheme for maintaining latch-up immunity in micron and sub-micron CMOS circuits.