0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography

A high performance CMOS process using mix e-beam/optical lithography has been developed for VLSI applications. The 0.5 μm channel devices are fabricated with shallow N+ and P+ source/drain junctions. Self-aligned silicide on gate and diffusions reduces the sheet resistance to 5 ohm/sq.. The shallow retrograde N-well formed by multiple high energy phosphorous implants without a drive-in a allows the use of thin P/P+ epi for latch-up control.