A 50 Nsec 64 K Bit CMOS Eeprom with 200μsec Programming

A 50 nsec 64K bit CMOS EEPROM utilizing Dual Control Gate cells (DC cells) has been developed featuring programming times as fast as 200 μsec. A new high speed sense amplifier system has been implemented that consists of reliability test circuits and new circuitry that increases the amount of data charge in the memory cell. The chip is fabricated by n-well CMOS triple polysilicon process with two-level aluminum metallization. A chip size of 5.95 x 4.88 mm^2 with 11 x 14 μm^2 cell size has been achieved by using the new DC cell (1) with rather conservative 2.0 μm design rule.