Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield

We study the yield improvements of mixed/split gate designs in 45 nm FinFET technology. The original contributions of this paper are: fast statistical analysis for FinFET designs including 6T and 8T column- decoupled designs, and the proposed low-voltage 6T- column-decoupled SRAM cell using stacked_and FinFET devices. Sensitivities of the cell yield to device design uncertainties and process variations are evaluated. Statistical analysis indicates that column-decoupled cells can help lower the stability requirement on the cell beta ratio and hence relax the design limitations with FinFET technology such as quantization penalties. Furthermore, physical cell image diagrams show that the 6T-decoupled cell suffers very small area penalties compared to the traditional double gate designs. Fast statistical analysis techniques are used to estimate yield trend. Numerical device/circuit mix-mode simulations support the predicted trends. Threshold voltage variations due to random dopant fluctuations are estimated using a macroscopic modeling method. The impact of fin-height variations is also evaluated.