Optimal Low Power Design of DDR2 Memory Interface for Compact Ultra Mobile Personal Computer (UMPC) Applications

In this paper, we suggest a topology design optimization of the address/command signals for DDR2 memory module to minimize the overshoot in waveforms when the 0.9V V
_TT
terminations are removed for power saving and cost reduction. Simulations in frequency domain and time domain are performed for optimal signal integrity, and the optimized designs are verified by measurements.